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ESSI Programming Model
This section discusses the ESSI registers and describes their bits. Section 7.6 , GPIO Signals and
Registers , on page 7-34 covers ESSI GPIO.
7.5.1 ESSI Control Register A (CRA)
The ESSI Control Register A (CRA) is one of two 24-bit read/write control registers that direct
the operation of the ESSI. CRA controls the ESSI clock generator bit and frame sync rates, word
length, and number of words per frame for serial data.
23
11
22
SSC1
10
21
WL2
9
20
WL1
8
19
WL0
7
18
ALC
6
17
5
16
DC4
4
15
DC3
3
14
DC2
2
13
DC1
1
12
DC0
0
PSR
PM7
PM6
PM5
PM4
PM3
PM2
PM1
PM0
—Reserved bit; read as 0; write to 0 for future compatibility.
(ESSI0 X:$FFFFB5, ESSI1 X:$FFFFA5)
Figure 7-2. ESSI Control Register A(CRA)
Table 7-3. ESSI Control Register A (CRA) Bit Definitions
Bit Number
23
22
Bit Name
SSC1
Reset Value
0
0
Description
Reserved. Write to 0 for future compatibility.
Select SC1
Controls the functionality of the SC1 signal. If SSC1 is set, the ESSI is
configured in Synchronous mode (the CRB synchronous/asynchronous bit
(SYN) is set), and transmitter 2 is disabled (transmit enable (TE2) = 0), then
the SC1 signal acts as the transmitter 0 driver-enabled signal while the SC1
signal is configured as output (SCD1 = 1). This configuration enables an
external buffer for the transmitter 0 output. If SSC1 is cleared, the ESSI is
configured in Synchronous mode (SYN = 1), and transmitter 2 is disabled
(TE2 = 0), then the SC1 acts as the serial I/O flag while the SC1 signal is
configured as output (SCD1 = 1).
DSP56311 User’s Manual, Rev. 2
Freescale Semiconductor
7-13
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